This project implements a peer-to-peer file-sharing system consisting of two primary components: the Server and the Client. The system facilitates direct file sharing between clients connected to the server and allows them to communicate and exchange files seamlessly. 

GitHub

GitHub

This Verilog project implements a 64-bit Carry Look-Ahead Adder (CLA-64). The design is hierarchical, consisting of Partial Full Adders (PFA) and 4-bit Carry Look-Ahead Adders (CLA-4bit) as building blocks. The final 64-bit adder is created by instantiating four instances of CLA-16bit. 

GitHub

This Verilog project implements a Pipelined Ripple Carry Adder (PRCA) using behavioral modeling. The PRCA is a type of adder that utilizes pipeline registers to improve performance by breaking down the addition process into stages. Each stage consists of a full adder and a flip-flop, forming a pipeline to enable parallel processing of input bits.

GitHub